1. Field of the Invention
The present invention relates to a semiconductor memory serving as an SRAM mounted on a CMOS gate array.
2. Description of the Prior Art
When an SRAM is to be mounted on a CMOS gate array, a full CMOS SRAM is conventionally constructed. Therefore, when a CMOS gate array shown in FIG. 1 is used, one memory cell is constituted by a unit cell consisting of four n-channel transistors, four p-channel transistors and a substrate contact portion.
Note that the two p-channel transistors of the unit cell of the CMOS gate array are left unused.
However, when eight transistors, i.e., two pairs of n-channel transistors and two pairs of p-channel transistors are occupied for one memory cell as described above, a memory cell area is too large to obtain a large capacity.